The demand for ever-faster computers requires that state-of-the-art microprocessors execute instructions in the minimum amount of time. Microprocessor speeds have been increased in a number of different ways, including increasing the speed of the clock that drives the processor, reducing the number of clock cycles required to perform a given instruction, implementing pipeline architectures, and increasing the efficiency at which internal operations are performed. This last approach usually involves reducing the number of steps required to perform an internal operation.
Efficiency is particularly important in mathematical calculations, particularly floating point calculations. However, with the trend to increase the integer unit size to 64 bits, many of the problems that previously present only in floating point units are now also occurring in the integer unit. Some mathematical operations, such as multiplication and division, cause significant delays during program execution. Many attempts have been made to design multipliers that have the least number of gate delays possible and that consume the least amount of chip area. A conventional multiplier has a first stage that contains a partial products generating circuit that receives a multiplicand and a multiplier and generates a plurality of partial products therefore. The partial products are then summed in a second stage that contains either a tree adder or an array adder.
For example, the floating point unit in a microprocessor may contain a multiplier that accepts a 64-bit multiplicand and a 64-bit multiplier and generates 64 partial products, P0 through P63. P0 is the partial product formed by multiplying the multiplicand by the least significant bit of the multiplier. P63 is the partial product formed by multiplying the multiplicand by the most significant bit of the multiplier. Each partial product is a 64-bit value.
The 64 partial products may then be summed in tree structure, such as a Wallace tree. The tree structure may comprise a first level of 64/3=22 carry-save adders (CSA), each of which adds three 64-bit partial products to generate an output containing a 74-bit sum and a 74-bit carry value. The 22×2=44 outputs of the first level of CSAs are then summed by a second level of 22/3=15 CSAs, each of which adds three outputs from the first level to generate an output containing a 74-bit sum and a 74-bit carry value. The tree structure continues to narrow in subsequent levels of CSAs, wherein each level sums the outputs of the preceding level of CSAs. The 128-bit sum and 128-bit carry outputs of a final CSA are then added in a carry propagate adder (CPA) stage to produce a 64-bit sum output and a single carry bit output. Six levels of CSAs are required to reduce the 64 partial products to the output of the final CSA. Thus, the delay through the tree structure is six times the delay of an individual carry-save adder.
Alternatively, the 64 partial products may be summed in an array of 64 CSAs. In a 64 CSA array, a first CSA may add, for example, the two least significant partial products, P0 and P1. A second CSA then adds the third partial product, P2, to the output of the first CSA. A third CSA then adds the fourth partial product, P3, to the output of the second CSA. The process continues until a sixty-third CSA adds the sixty-fourth partial product, P63, to the output of the sixty-second CSA. Finally, the 64-bit sum and 64-bit carry outputs of the sixty third final CSA are added in a carry propagate adder (CPA) stage to produce a 64-bit sum output and a single carry bit output. Thus, the delay through the array structure is sixty-three times the delay of an individual carry-save adder.
Both the array structure and the tree structure have distinct advantages and disadvantages. The array structure has a comparatively large delay, one for each CSA. However, the array structure is fairly easy to lay out on a silicon wafer because of the repeating pattern of each succeeding CSA. The gate delay is constant for each stage and can be effectively minimized.
The tree structure has a comparatively small delay, at least theoretically. However, the tree structure is limited by the asymmetric routing of its signal lines. When the tree structure is laid out on a silicon wafer and is compressed into a more or less rectangular shape in order to minimize wafer space, there is a large amount of non-uniform line length and non-constant routing density. These problems tend to offset the speed performance realized by the reduced number of gate delays.
Therefore, there is a need in the art for improved microprocessor that execute mathematical operations more rapidly. In particular, there is a need for an improved multiplier that has the simple design advantages of an array structure for summing partial products, but which does not suffer the excessive delays associated with conventional array structures.